This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-088705, filed Mar. 28, 2000; and No. 2001-086273, filed Mar. 23, 2001, the entire contents of both of which are incorporated herein by reference.
The present invention relates to a tester for a semiconductor device for testing a semiconductor device which is generally assembled, for example, in a package.
Generally, in the case where a semiconductor device assembled in a package is tested, the semiconductor device is attached on a jig provided on a test board. In this state, the semiconductor device and a test board are electrically connected to test the semiconductor device.
FIG. 16 is a view showing a conventional first type test board. The test board 1 is provided with a socket 2. A semiconductor device 3 is attached on this socket 2. On the test board located inside of this socket 2, a connection portion 4 is provided which has a plurality of pads for connection. On this connection portion 4, an anisotropic conductive sheet 5 is arranged. The anisotropic conductive sheet 5 is constituted in such a manner that a plurality of metal fine lines 5a are arranged in correspondence to the pad, for example, in the insulating silicone rubber. One end of the metal fine line 5a is exposed to the surface of the insulating silicone rubber while the other end is exposed to the rear surface of the insulating silicone rubber.
FIGS. 17A and 17B are views showing a connection portion 4 provided on the test board 1. On the surface of the connection portion 4, a plurality of pads are provided. These pads are connected to pins for connection provided on the semiconductor device 3. In the case of this example, the semiconductor device to be measured is, for example, a pin grid array, or a ball grid array. On the surface of the connection portion 4, a plurality of power source pads 6, ground pads 7 and signal pads 8 are arranged. These power source pads 6, ground pads 7 and signal pads 8 are respectively connected to the power source layer 9, the ground wiring layer 10, and signal wiring layer 11 provided inside of the test board 1.
In the above structure, each pin of the semiconductor device 3 attached on the socket 2 is connected to the power source pads 6, the ground pads 7 and the signal pads 8 respectively via the anisotropic conductive sheet 5 so that a predetermined test is carried out in this state.
By the way, on the above first type test board, the power source pads 6, the ground pads 7 and the signal pads 8 provided on the connection portion 4 are arranged in correspondence to the locations of the power source pins and the ground pins determined for each of the semiconductor devices 3. Therefore, in the case where the positions of the power source pins and the ground pins of the semiconductor device to be measured do not coincide with the positions of these pads, it is required to manufacture a test board corresponding to the pins of the semiconductor device to be measured. As a consequence, a cost required for the test becomes high. Besides, since it is required to prepare a large number of dedicated test boards corresponding to the semiconductor device, a large space must be secured for conserving these test boards.
Furthermore, still two types of test boards are available as another embodiment. A second type test board is such that a socket to which the semiconductor device is attached is directly provided on the test board. On this socket, a contact connected to the semiconductor device is provided. This contact is electrically connected to the test board. In the case of the second type test board, there is a problem similar to the test board shown in FIGS. 16 and 17. That is, in the case where the power source pin and the ground pin of the semiconductor device as an object to be measured do not coincide with the position of the contact provided on the socket, it is required to prepare a test board corresponding to the pin of the semiconductor device to be measured. Consequently, the cost required for the test becomes high. Besides, since it is required to prepare a large number of dedicated test boards corresponding to the semiconductor device, a large space must be secured for conserving these test boards.
A third type test board has a first substrate and a second substrate as test boards, and a contact ring provided between the first and the second substrates. The first substrate has a plurality of electrode pads as a signal pad, a power source pad, and a ground pad. The second substrate has a socket on which the semiconductor device is attached on the surface thereof. On this socket, a plurality of contacts are provided which are connected to the semiconductor device. On the rear surface of the second substrate, a plurality of electrode pads are arranged which are electrically connected to each of the contacts. The contact ring has a pin comprising a plurality of conductive rubbers or conductive springs in the insulating substrate. One end of these pins is exposed to the surface of the contact ring while the other end thereof is exposed to the rear surface of the contact ring. The second substrate is electrically connected to the first substrate via the contact ring. That is, in the state in which the contact ring is arranged between the first substrate and the second substrate, the contact rings are attached and the first and the second substrates are pressed against the contact rings. In this state, the electrode pad arranged on the rear surface of the second substrate is connected to the electrode pad corresponding to the first substrate via the pin of the contact ring.
On the above third type test board, the second substrate is constituted of the insulating resin having a thickness of, for example, 3 mm. A plurality of conductive metals having a length equivalent to the thickness of the substrate is provided in the second substrate. One end of the conductive metal is connected to a contact in the socket while the other end thereof is connected to the electrode pad arranged on the rear surface of the second substrate. Furthermore, the contact ring is constituted of an insulating resin having a thickness of, for example, 12 mm. In this contact ring, a pin is provided which comprises a conductive rubber or a conductive spring having a thickness of, for example, 14 mm. Consequently, one and the other end of these pins are projected by 1 mm from the surface and the rear surface of the insulating substrate. In this manner, in the case of the third type test board, the pin of the semiconductor device is connected to the electrode pad of the first substrate via a long conductive metal and a pin, these long conductive metal and pins have a large impedance, particularly large inductance. Consequently, in the third type test board, transmission delay of signals is generated with this inductance so that it is difficult to conduct tests using a high-speed signal of tens of MHz or more.
An object of the present invention is to provide a tester for a semiconductor device which can reduce cost required for the test of the semiconductor device and can decrease a space for conserving the test instrument, the tester being capable of testing the device at a high speed.
An object of the present invention can be attained by the following structure.
There is provided a tester for a semiconductor device, the apparatus comprising: a test board having a first electrode pad, a first power source pad and a second power source pad, the first electrode pad being arranged in correspondence to a signal pin of the semiconductor device, the first and the second power source pads being arranged in separation from the first electrode pad; a first intermediate board having a third power source pad, a fourth power source pad and a first hole, the third power source pad corresponding to the first power source pin of the semiconductor device, the fourth power source pad being electrically connected to the third power source pad and corresponding to the first power source pad of the test board, the first hole corresponding to the second power source pin of the semiconductor device; a second intermediate board having a fifth power source pad, a sixth power source pad and a second hole, the fifth power source pad being arranged between the first intermediate board and the test board and being in correspondence to the second power source pin of the semiconductor device, the sixth power source pad being electrically connected to the fifth power source pad and being in correspondence to the second power source pad of the test board, the second hole being in correspondence to the fourth power source pad of the first intermediate board; a first conductive sheet arranged mutually between the first intermediate board and the semiconductor device, the first conductive sheet electrically connecting the first power source pin of the semiconductor and the third power source pad of the first intermediate board; a second conductive sheet arranged between the first intermediate board and the second intermediate board, the second conductive sheet electrically connecting the second power source pin of the semiconductor device and the fifth power source pad of the second intermediate board via the first hole of the first intermediate board and the first conductive sheet; and a third conductive sheet arranged between the second intermediate board and the test board, the third conductive sheet electrically connecting the sixth power source pad of the second intermediate board and the second power source pad of the test board, and electrically connecting the fourth power source pad of the first intermediate board and the first power source pad of the test board via the second hole of the second intermediate board and the second conductive sheet.
Furthermore, the object of the present invention is attained with the following device.
There is provided a tester for a semiconductor device, the apparatus comprising: a test board having a first electrode pad, a first power source pad and a second power source pad, the first electrode pad being arranged in correspondence to a signal pin of the semiconductor device, the first power source pad and the second power source pad being arranged in separation from the first electrode pad, and an intermediate board having a third power source pad, a fourth power source pad, a fifth power source pad, and a sixth power source pad, the third power source pad corresponding to the first power source pin of the semiconductor device, the fourth power source pad being electrically connected to the third power source pad and corresponding to the first power source pad of the test board, the fifth power source pad corresponding to the second power source pin of the semiconductor device, the sixth power source pad being electrically connected to the fifth power source pad and corresponding to the second power source pad of the test board.
Furthermore, the object of the present invention is attained with the following device.
There is provided a tester for a semiconductor device, the apparatus comprising: an intermediate board having s first electrode pad, a second electrode pad and a test circuit, the first electrode pad being arranged in correspondence to a signal pin of the semiconductor device on a first surface of the intermediate board, the test circuit being electrically connected to the first electrode pad, the second electrode pad being arranged on a second surface on the opposite side of the first surface of the intermediate board and being electrically connected to the test circuit; a test board having a third electrode pad arranged in correspondence to the second electrode pad of the intermediate board; and a conductive sheet being arranged between the intermediate board and the test board, the conductive sheet electrically connecting the second electrode pad of the intermediate board and the third electrode pad of the test board.
Furthermore, an object of the present invention can be attained with the following device.
There is provided a tester for a semiconductor device, the apparatus comprising: a test board having a first electrode pad and a first power source pad, the first electrode pad being arranged in correspondence to a signal pin of the semiconductor device, the first power source pad being arranged in separation from the first electrode pad; and an intermediate board having a second power source pad, a third power source pad, a second electrode pad and a third electrode pad, the second power source pad being electrically connected to the power source pin of the semiconductor device, the third power source pad being electrically connected to the second power source pad and being connected to the first power source pad of the test board, the second electrode pad being connected to the signal pin of the semiconductor device, the third electrode pad being electrically connected to the second electrode pad and being connected to the first electrode pad of the test board.
According to the present invention, the cost required for the test of the semiconductor device can be decreased while a space for conserving the test instrument can be decreased. Furthermore, a high-speed test is made possible which can decrease the transmission delay of the signal.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.